Computing of the Future - Energy-Efficient Large-Scale High-Performance Computing
General Information
What will Computing be like in 20 years? What is the future beyond the end of the current roadmap for CMOS microprocessors? The phenomenal advances in computing technology over the past two decades were enabled by Dennard scaling, whereby the exponential improvements in power efficiency and performance and cost-effectiveness of silicon technology tracked Moore’s Law improvements in integrating more devices on each chip. As we approach atomic scale lithography, the end of Dennard scaling puts future growth of the computing industry in jeopardy. Multicore has provided a temporary respite from stagnation of CPU clock frequencies, but creates daunting challenges to programmability, and drives today’s system architectures towards extreme levels of unbalanced communication-to-computation ratios!
This workshop will promote discussions on a comprehensive strategy that directly addresses the challenges of power-density, bandwidth limits, programmability, and interconnect technologies. One of the central goals of the workshop is to discuss methods to eliminate the growing system imbalance performance gap by creating a new computing platform where bandwidth is uniformly plentiful across the entire system and is not traded off the power budget. A system with such uniform system-wide bandwidth offers significantly simpler optimization strategies for software architects that address many of the programmability concerns for multicore chips and massively parallel computing platforms. Addressing the three key areas of energy consumption, bandwidth scaling, and programmability will enable continued exponential improvements in power-efficiency, performance, and cost-effectiveness that drive the computing industry for the next 20 years.
This workshop addresses key opportunities and challenges of Future Computing, in the architecture, nanotechnologies, interconnection, and systems areas.
Topics
• Applications and Architectures of Future Computing Systems
• Nanotechnologies beyond CMOS (nanophotonics, nanoelectronics, nanomagnetics)
• Novel Interconnection
| Day: | Friday, February 29 |
|---|---|
| 7:30 am | Breakfast |
| 8:15 am | Registration |
| 9:00 am | Workshop Introduction, Overview, and Goals Final Overview S.J. Ben Yoo, UC Davis |
| 9:30 am | Results from the Zettaflops Workshop 2007 Presentation |
| 10:00 am | Tera-scale Computing - motivation and challenges Presentation |
| 10:30 am | Break |
| 11:00 am | Hardware Design Constraints for Power Efficient Scientific Computing Presentation |
| 11:30 am | The Future Evolution of High-Performance Microprocessors Presentation |
| 12:00 Noon |
Presentation |
| 12:30 pm | Lunch |
| 1:30 pm |
Presentation |
| 2:00 pm | IntraChip Optical Networks for a Future Supercomputer-on-a-Chip Presentation |
| 2:30 pm | Plasmonics: Bridging nanoelectronics and nanophotonics Presentation |
| 2:45 pm | Nanowires: Massively Parallel Interconnects Presentation |
| 3:00 pm | An Overview of NSA Advanced Computing System Program Lance Janeckis, Information Defence Analysis |
| 3:20 pm | Break |
| 3:50 pm | Discussions: Computing of the Future Moderated by S. J. Ben Yoo, UC Davis |
| 5:30 pm | Social |
| 6:00 - 8:00 pm | Dinner Banquet |
| Day: | Saturday March 1, 2008 (Optional Lab Tour) |
|---|---|
| 8:00 am | Depart Crowne Plaza SFO |
| 9:30 am | Arrive at UC Davis Campus |
| 9:40 am | Northern California Nanotechnology Center Tour Frank Yaghmaie, UC Davis |
| 10:00 am | 188 core ASAP II processor chip demo Bevan Baas, UC Davis |
| 10:20 am | Nano-wire device demo Saif Islam, UC Davis |
| 10:35am | Photonic Integrated System-on-a-Chip Demo S.J. Ben Yoo, UC Davis |
| 10:50 am | Spintronic Devices Tour Kaui Lui, UC Davis |
| 11:05 am | Depart Davis for Stanford |
| 12:40 pm | Lunch at Stanford |
| 1:20 pm | Photonic Interconnects and Plasmonics David A. B. Miller (or Staff), Stanford |
| 2:20 pm | Depart Stanford for Crowne Plaza Hotel, SFO |
| 2:50 pm | Crowne Plaza Hotel, SFO Arrival |